1. Field of the Disclosure
The present disclosure relates to electronic devices and processes for forming them, and more particularly to electronic devices including epitaxially formed source/drain regions.
2. Description of the Related Art
The etch of source/drain regions can be used to clean source/drain regions or to form recesses within which subsequent epitaxial layer can be formed. The etch process may be used on NMOS and PMOS transistors locations independent of each other. Formation of a protective layer, such as oxide layer, over the transistor locations not being processed allows the processing on exposed transistor locations to proceed. The use of timed etches with the use of protective layers have shown to result in surface loading effects that cause locally increased etch rates that are hard to control and result in recess variations amongst source/drain regions. These recess variations can be tolerable where bulk substrates are used, but can result in bottoming-out where relatively thin active layers are available, such as with silicon-on-insulator substrates. Another problem occurs during removal of the layer used to protect wafer portions not being processed because the exposed transistor locations, which were just etched, are further subjected to the chemistries used to remove the protective layer thereby potentially damaging the exposed transistor locations. A process of providing greater control in the etching of source/drain regions to overcome these problems would be useful.
It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments.